Software Interrupt Event Register (Exti_Swier1); Pending Register (Exti_Pr1) - STMicroelectronics RM0365 Reference Manual

Advanced arm-based 32-bit mcus

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The external wakeup lines are edge-triggered. No glitches must be generated on these

lines. If a falling edge on an external interrupt line occurs during a write operation to the

EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this case, both

generate a trigger condition.r

Software interrupt event register (EXTI_SWIER1)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 29:23 Reserved, must be kept at reset value.

Bits 22:0 SWIERx: Software interrupt on line x (x = 22 to 0)

Address offset: 0x14

Reset value: undefined

Bit 31 Reserved, must be kept at reset value.

Bit 30 SWIERx: Software interrupt on line x (x = 30)

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when

it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt

request generation.

This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by

writing a '1' into the bit).

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when

it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt

request generation.

This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'

into the bit).

DocID025202 Rev 7

Interrupts and events

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