RM0365
Bit 3 OPM: One pulse mode
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
20.4.2
TIM1 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
OIS4
OIS3N
OIS3
rw
rw
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
OIS2N
OIS2
OIS1N
rw
rw
rw
rw
24
23
22
Res.
MMS2[3:0]
rw
rw
8
7
6
OIS1
TI1S
rw
rw
rw
DocID025202 Rev 7
Advanced-control timers (TIM1)
21
20
19
Res.
OIS6
rw
rw
5
4
3
MMS[2:0]
CCDS
CCUS
rw
rw
rw
18
17
16
Res.
OIS5
rw
rw
2
1
0
Res.
CCPC
rw
rw
516/1080
549
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