Flexible static memory controller (FSMC)
Bit
number
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit number
31-30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
245/1080
Table 58. FMC_BCRx bit fields
Bit name
Reserved
0x000
CCLKEN
As needed
CBURSTRW
0x0 (no effect in asynchronous mode)
Reserved
0x0
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD
0x1 for mode B, 0x0 for mode 2
WAITEN
0x0 (no effect in asynchronous mode)
WREN
As needed
WAITCFG
Don't care
WRAPMOD
0x0
WAITPOL
Meaningful only if bit 15 is 1
BURSTEN
0x0
Reserved
0x1
FACCEN
0x1
MWID
As needed
MTYP
0x2 (NOR Flash memory)
MUXEN
0x0
MBKEN
0x1
Table 59. FMC_BTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x1 if extended mode is set
DATLAT
Don't care
CLKDIV
Don't care
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD
Don't care
Duration of the access first phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.
DocID025202 Rev 7
Value to set
Value to set
RM0365
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