STMicroelectronics RM0365 Reference Manual page 131

Reset and clock control (RCC)
Bits 13:11 PPRE2: APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB2 clock (PCLK).
Bits 10:8 PPRE1: APB Low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB1 clock (PCLK).
Bits 7:4 HPRE: HLCK prescaler
Set and cleared by software to control the division factor of the AHB clock.
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the
Bits 3:2 SWS: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
Bits 1:0 SW: System clock switch
Set and cleared by software to select SYSCLK source.
Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case
of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
131/1080
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
AHB clock. Refer to section
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
Read operations on page 59
DocID025202 Rev 7
RM0365
for more details.