I2C Clock Requirements; Mode Selection - STMicroelectronics RM0365 Reference Manual

RM0365
I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled
by setting the driving capability control bits for SCL and SDA in
configuration register 1
28.4.2

I2C clock requirements

The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
t
I2CCLK < (tLOW - tfilters ) / 4 and
with:
t
LOW: SCL low time and tHIGH : SCL high time
t when enabled, sum of the delays brought by the analog filter and by the digital filter.
filters:
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x t
The PCLK clock period t
t
PCLK < 4/3 tSCL
with t
SCL: SCL period
Caution: When the I2C kernel is clocked by PCLK. PCLK must respect the conditions for t
28.4.3

Mode selection

The interface can operate in one of the four following modes:
•
Slave transmitter
•
Slave receiver
•
Master transmitter
•
Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition and ends with a STOP condition.
Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection can be enabled or disabled
by software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.
(SYSCFG_CFGR1).
must respect the following conditions:
I2CCLK
t
I2CCLK < tHIGH
must respect the following condition:
PCLK
DocID025202 Rev 7
Inter-integrated circuit (I2C) interface
Section 11.1.1: SYSCFG
I2CCLK
.
.
I2CCLK
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