STMicroelectronics RM0365 Reference Manual page 203

Direct memory access controller (DMA)
Offset Register
0x40 Reserved
DMA_CCR4
0x44
Reset value
DMA_CNDTR4
0x48
Reset value
DMA_CPAR4
0x4C
Reset value 0
DMA_CMAR4
0x50
Reset value 0
0x54 Reserved
DMA_CCR5
0x58
Reset value
DMA_CNDTR5
0x5C
Reset value
DMA_CPAR5
0x60
Reset value 0
DMA_CMAR5
0x64
Reset value 0
0x68 Reserved
DMA_CCR6
0x6C
Reset value
DMA_CNDTR6
0x70
Reset value
DMA_CPAR6
0x74
Reset value 0
DMA_CMAR6
0x78
Reset value 0
0x7C Reserved
DMA_CCR7
0x80
Reset value
DMA_CNDTR7
0x84
Reset value
203/1080
Table 39. DMA register map and reset values (continued)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DocID025202 Rev 7
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0
0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
RM0365
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0