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System window watchdog (WWDG)
25.4.2
Configuration register (WWDG_CFR)
Address offset: 0x04
Reset value: 0x0000 007F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
Bits 8:7 WDGTB[1:0]: Timer base
The time base of the prescaler can be modified as follows:
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared to the downcounter.
25.4.3
Status register (WWDG_SR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by
software by writing '0'. A write of '1' has no effect. This bit is also set if the interrupt is not
enabled.
711/1080
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
EWI
rs
00: CK Counter Clock (PCLK div 4096) div 1
01: CK Counter Clock (PCLK div 4096) div 2
10: CK Counter Clock (PCLK div 4096) div 4
11: CK Counter Clock (PCLK div 4096) div 8
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
WDGTB[1:0]
rw
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
DocID025202 Rev 7
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
W[6:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0365
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
Res.
EWIF
rc_w0
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