Table 62. Fmc_Btrx Bit Fields; Table 63. Fmc_Bwtrx Bit Fields - STMicroelectronics RM0365 Reference Manual

RM0365
Bit No.
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Table 61. FMC_BCRx bit fields (continued)
Bit name
MUXEN 0x0
MBKEN 0x1

Table 62. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x2
DATLAT 0x0
CLKDIV 0x0
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.

Table 63. FMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x2
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 0.
DocID025202 Rev 7
Flexible static memory controller (FSMC)
Value to set
Value to set
Value to set
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