Spix_I 2 S Prescaler Register (Spix_I2Spr) - STMicroelectronics RM0365 Reference Manual

RM0365
2
30.9.9 SPIx_I
Address offset: 0x20
Reset value: 0000 0010 (0x0002)
Bits 15:10 Reserved: Forced to 0 by hardware
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I
mode.
It is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: Real divider value is = I2SDIV *2
1: Real divider value is = (I2SDIV * 2)+1
Refer to Section 30.7.4 on page 937
Note: This bit should be configured when the I
mode.
It is not used in SPI mode.
Bits 7:0 I2SDIV[7:0]: I
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 30.7.4 on page 937
Note: These bits should be configured when the I
in master mode.
They are not used in SPI mode.
S prescaler register (SPIx_I2SPR)
2
S linear prescaler
DocID025202 Rev 7
Serial peripheral interface / inter-IC sound (SPI/I2S)
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
2
S is disabled. They are used only when the I
2
S is in master
2
S is in master
2
S is
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