Supported Memories And Transactions; Table 52. Nor Flash/Psram: Example Of Supported Memories And Transactions - STMicroelectronics RM0365 Reference Manual

RM0365
FMC signal name
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits (26 address lines).
14.5.2

Supported memories and transactions

Table 52
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.
Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
16-Bit
Table 51.
I/O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e.
O
O
O
O
I
Byte lane output. Byte 0 and Byte 1 control (upper and lower byte
O
below shows an example of the supported devices, access modes and
Table 52. NOR Flash/PSRAM: Example of supported memories and
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
DocID025202 Rev 7
Flexible static memory controller (FSMC)
multiplexed I/O PSRAM (continued)
A[15:0] and data D[15:0] are multiplexed on the databus)
Output enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FMC
transactions
AHB
Memory
R/W data
data size
size
R 8 16
W 8 16
R 16 16
W 16 16
R 32 16
W 32 16
R - 16
R 8 16
R 16 16
R 32 16
Function
CRAM))
Write enable
enable)
Allowed/
not Comments
allowed
Y
N
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
N Mode is not supported
N
Y
Y
-
-
-
-
-
-
-
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