Exti Registers; Interrupt Mask Register (Exti_Imr1); Event Mask Register (Exti_Emr1) - STMicroelectronics RM0365 Reference Manual

Interrupts and events
13.3 registers
EXTI
Refer to
The peripheral registers have to be accessed by words (32-bit).
13.3.1

Interrupt mask register (EXTI_IMR1)

Address offset: 0x00
Reset value: 0x1F80 0000 (See note below)
31 30 29
Res. MR30 Res. MR28
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15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 28:0 MRx: Interrupt Mask on external/internal line x
Note: The reset value for the internal lines (23, 24, 25, 26, 27 and 28) is set to '1' in order to
enable the interrupt by default.
13.3.2

Event mask register (EXTI_EMR1)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. MR30 Res. MR28
rw
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
217/1080
Section 2.1 on page 42
28 27 26 25
MR27 MR26 MR25
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12 11 10 9
MR11 MR10 MR9
rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 MRx: Interrupt Mask on external/internal line x (x = 30)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 29 Reserved, must be kept at reset value.
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
28 27 26 25
MR27 MR26 MR25
rw rw rw rw
12 11 10 9
MR11 MR10 MR9
rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
for a list of abbreviations used in register descriptions.
24 23 22
MR24 MR23 MR22
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8 7 6
MR8 MR7 MR6
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24 23 22
MR24 MR23 MR22
rw rw rw
8 7 6
MR8 MR7 MR6
rw rw rw
DocID025202 Rev 7
21 20 19 18
MR21 MR20 MR19 MR18
rw rw rw rw
5 4 3 2
MR5 MR4 MR3 MR2
rw rw rw rw
21 20 19 18
MR21 MR20 MR19 MR18
rw rw rw rw
5 4 3 2
MR5 MR4 MR3 MR2
rw rw rw rw
RM0365
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw