RM0365
Figure 47. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)
1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.
Bit No.
31-21
20
19
18-15
14
13
12
11
Table 69. FMC_BCRx bit fields
Bit name
Reserved
0x000
CCLKEN
As needed
CBURSTRW
No effect on synchronous read
Reserved
0x0
EXTMOD
0x0
to be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise
WREN
no effect on synchronous read
WAITCFG
to be set according to memory
DocID025202 Rev 7
Flexible static memory controller (FSMC)
Value to set
258/1080
286
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