Tim16/Tim17 Prescaler (Timx_Psc); Tim16/Tim17 Auto-Reload Register (Timx_Arr) - STMicroelectronics RM0365 Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)
Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
22.6.9

TIM16/TIM17 prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in "reset mode").
22.6.10

TIM16/TIM17 auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
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Bits 15:0 ARR[15:0]: Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the
and behavior.
The counter is blocked while the auto-reload value is null.
685/1080
12 11 10 9
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12 11 10 9
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Section 22.4.1: Time-base unit on page 623
DocID025202 Rev 7
8 7 6 5
PSC[15:0]
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CK_PSC
8 7 6 5
ARR[15:0]
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4 3 2
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/ (PSC[15:0] + 1).
4 3 2
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for more details about ARR update
RM0365
1 0
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1 0
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