Spi Rx Crc Register (Spix_Rxcrcr); Spi Tx Crc Register (Spix_Txcrcr) - STMicroelectronics RM0365 Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
30.9.6

SPI Rx CRC register (SPIx_RXCRCR)

Address offset: 0x14
Reset value: 0x0000
15 14 13
r r r
Bits 15:0 RXCRC[15:0]: Rx CRC register
When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of
the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1
register is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL
bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY Flag is set could return an incorrect value.
30.9.7

SPI Tx CRC register (SPIx_TXCRCR)

Address offset: 0x18
Reset value: 0x0000
15 14 13
r r r
Bits 15:0 TxCRC[15:0]: Tx CRC register
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is
written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY flag is set could return an incorrect value.
955/1080
12 11 10 9
r r r r
These bits are not used in I
12 11 10 9
r r r r
These bits are not used in I
DocID025202 Rev 7
8 7 6 5
RxCRC[15:0]
r r r r
2
S mode.
8 7 6 5
TxCRC[15:0]
r r r r
2
S mode.
RM0365
4 3 2 1
r r r r
4 3 2 1
r r r r
0
r
0
r