STMicroelectronics RM0365 Reference Manual page 193

Direct memory access controller (DMA)
Table 37. STM32F302x6/8 summary of DMA1 requests for each channel (continued)
Peripheral Channel 1
TIM15 -
TIM16 -
TIM17_CH1
TIM17
TIM17_UP
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 or
SYSCFGR3 register. For more details, please refer to
on page 172.
DMA2 controller (available only in STM32F302xB/C/D/E)
The five requests from the peripherals (TIMx (x= 6), ADCx (x=2), SPI/I2S3, UART4,
DAC_Channel[1,2] ) are simply logically ORed before entering the DMA2, this means that
only one request must be enabled at a time. Refer to
request mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
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Channel 2 Channel 3
- -
TIM16_CH1
-
TIM16_UP
- -
Section 11.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1)
DocID025202 Rev 7
Channel 4 Channel 5
TIM15_CH1
TIM15_UP
-
TIM15_TRIG
TIM15_COM
- -
- -
Figure 26: STM32F302xB/C DMA2
RM0365
Channel6 Channel7
- -
TIM16_CH1
-
(1)
TIM16_UP
TIM17_CH1
-
TIM17_UP
(1)