Ahb Peripheral Clock Enable Register (Rcc_Ahbenr) - STMicroelectronics RM0365 Reference Manual

RM0365
Bit 2 TIM4RST: TIM4 timer reset (STM32F302xB/C devices only)
Set and cleared by software.
Bit 1 TIM3RST: TIM3 timer reset (STM32F302xB/C devices only)
Set and cleared by software.
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
9.4.6

AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29
Res Res Res ADC12EN
15 14 13
Res Res Res
1. Only on STM32F302xDxE.
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 ADC12EN: ADC1 and ADC2 enable (ADC2 only in STM32F302xB/C)
Set and reset by software.
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 TSCEN: Touch sensing controller clock enable
Set and cleared by software.
Bit 23 IOPGEN: IO port G clock enable. (Only on STM32F302xDxE)
Set and cleared by software.
0: No effect
1: Reset TIM4
0: No effect
1: Reset TIM3
0: No effect
1: Reset TIM2
28 27 26 25
Res Res Res
rw
12 11 10 9
Res Res Res Res
0: ADC1 and ADC2 clock disabled
1: ADC1 and ADC2 clock enabled
0: TSC clock disabled
1: TSC clock enabled
0: IO port G clock disabled
1: IO port G clock enabled
24 23 22
IOPG
IOPF
TSCEN
(1)
EN
EN
rw rw rw
8 7 6
CRC
Res Res
EN
rw
DocID025202 Rev 7
Reset and clock control (RCC)
21 20 19 18
IOPE IOPD IOPC IOPB
EN EN EN EN
rw rw rw rw
5 4 3 2
FMC
FLITF SRAM
Res
(1)
EN EN
EN
rw rw rw
17 16
IOPH
IOPA
(1)
EN
EN
rw rw
1 0
DMA2 DMA1
EN EN
rw rw
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