Tim1 Capture/Compare Register 5 (Timx_Ccr5) - STMicroelectronics RM0365 Reference Manual

Advanced-control timers (TIM1)
Output compare mode
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 OC6M[3]: Output Compare 6 mode - bit 3
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 OC5M[3]: Output Compare 5 mode - bit 3
Bit 15 OC6CE: Output compare 6 clear enable
Bits 14:12 OC6M: Output compare 6 mode
Bit 11 OC6PE: Output compare 6 preload enable
Bit 10 OC6FE: Output compare 6 fast enable
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 OC5CE: Output compare 5 clear enable
Bits 6:4 OC5M: Output compare 5 mode
Bit 3 OC5PE: Output compare 5 preload enable
Bit 2 OC5FE: Output compare 5 fast enable
Bits 1:0 Reserved, must be kept at reset value.
20.4.23

TIM1 capture/compare register 5 (TIMx_CCR5)

Address offset: 0x58
Reset value: 0x0000 0000
31 30 29
GC5C3 GC5C2 GC5C1 Res.
rw rw rw
15 14 13
rw rw rw
545/1080
28 27 26 25
Res. Res. Res.
12 11 10 9
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DocID025202 Rev 7
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
CCR5[15:0]
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20 19 18 17
Res. Res. Res. Res.
4 3 2 1
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RM0365
16
Res.
0
rw