STMicroelectronics RM0365 Reference Manual page 618

RM0365
Table 121. TIM2/TIM3/TIM4 register map and reset values (continued)
Offset Register
TIMx_CNT
0x24
Reset value 0
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value 1
0x30
TIMx_CCR1
0x34
Reset value 0
TIMx_CCR2
0x38
Reset value 0
TIMx_CCR3
0x3C
Reset value 0
TIMx_CCR4
0x40
Reset value 0
0x44
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
Refer to
boundary addresses.
CNT[30:16]
(TIM2 only, reserved on the other timers)
0 0 0 0 0 0 0 0
ARR[31:16]
(TIM2 a only, reserved on the other timers)
1 1 1 1 1 1 1 1
CCR1[31:16]
(TIM2 only, reserved on the other timers)
0 0 0 0 0 0 0 0
CCR2[31:16]
(TIM2 only, reserved on the other timers)
0 0 0 0 0 0 0 0
CCR3[31:16]
(TIM2 only, reserved on the other timers)
0 0 0 0 0 0 0 0
CCR4[31:16]
(TIM2 only, reserved on the other timers)
0 0 0 0 0 0 0 0
Section 3.2.2: Memory map and register boundary addresses
General-purpose timers (TIM2/TIM3/TIM4)
0 0 0 0 0 0 0 0
0
1 1 1 1 1 1 1 1
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
0
DocID025202 Rev 7
CNT[15:0]
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
for the register
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0 0
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