Rtc Domain Reset; Figure 11. Simplified Diagram Of The Reset Circuit - STMicroelectronics RM0365 Reference Manual

RM0365
Software reset
The SYSRESETREQ bit in Cortex-M4
must be set to force a software reset on the device. Refer to the STM32F3xx/F4xx Cortex
M4 programming manual (PM0214) for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 13) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
9.1.3

RTC domain reset

The RTC domain has two specific resets that affect only the RTC domain
page 97).
An RTC domain reset only affects the LSE oscillator, the RTC, the Backup registers and the
RCC RTC domain control register
events occurs.
1. Software reset, triggered by setting the BDRST bit in the
(RCC_BDCR).
2. V
DD

Figure 11. Simplified diagram of the reset circuit

power-up if V has been disconnected when it was low.
BAT
DocID025202 Rev 7
®
F Application Interrupt and Reset Control Register
(RCC_BDCR). It is generated when one of the following
Reset and clock control (RCC)
Section 4: Option bytes.
(Figure 8 on
RTC domain control register
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