Figure 12. Stm32F302Xb/C Clock Tree - STMicroelectronics RM0365 Reference Manual

RM0365
The RCC feeds the Cortex
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex
clock (HCLK), configurable in the SysTick Control and Status Register.
1. For full details about the internal and external clock source characteristics, please refer to the "Electrical
characteristics" section in your device datasheet.
2. TIM1 can be clocked from the PLLCLKx2 running up to 144 MHz when the system clock source is the PLL.
Refer to
3. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable
factor (1, 2 or 4). When the programmable factor is '1', the AHB prescaler must be equal to '1'.
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System Timer (SysTick) external clock with the AHB clock

Figure 12. STM32F302xB/C clock tree

Section 9.2.10: Timers (TIMx)
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clock.
Reset and clock control (RCC)
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