Table 55. Fmc_Bcrx Bit Fields; Table 56. Fmc_Btrx Bit Fields - STMicroelectronics RM0365 Reference Manual

RM0365
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.
Bit
number
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0

Table 55. FMC_BCRx bit fields

Bit name
Reserved
CCLKEN
CBURSTRW
Reserved
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
MTYP
MUXEN
MBKEN

Table 56. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for read
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
ADDSET
Minimum value for ADDSET is 0.
DocID025202 Rev 7
Flexible static memory controller (FSMC)
0x000
As needed
0x0 (no effect in asynchronous mode)
0x0
Set to 1 if the memory supports this feature. Otherwise keep at
0.
0x1
0x0 (no effect in asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
Don't care
As needed
As needed, exclude 0x2 (NOR Flash memory)
0x0
0x1
Value to set
Value to set
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