Timx Capture/Compare Register 3 (Timx_Ccr3); Timx Capture/Compare Register 4 (Timx_Ccr4) - STMicroelectronics RM0365 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4)
21.4.15

TIMx capture/compare register 3 (TIMx_CCR3)

Address offset: 0x3C
Reset value: 0x0000
31 30 29 28
rw/r rw/r rw/r rw/r
15 14 13 12
rw/r rw/r rw/r rw/r
Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5)
Bits 15:0 CCR3[15:0]: Low Capture/Compare value
21.4.16

TIMx capture/compare register 4 (TIMx_CCR4)

Address offset: 0x40
Reset value: 0x0000
31 30 29
rw/r rw/r rw/r
15 14 13
rw/r rw/r rw/r
Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 )
Bits 15:0 CCR4[15:0]: Low Capture/Compare value
1.
2.
615/1080
27 26 25
CCR3[31:16] (depending on timers)
rw/r rw/r rw/r
11 10 9
rw/r rw/r rw/r
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3). The
TIMx_CCR3 register is read-only and cannot be programmed.
28 27 26 25
CCR4[31:16] (depending on timers)
rw/r rw/r rw/r rw/r
12 11 10 9
rw/r rw/r rw/r rw/r
if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2
register (bit OC4PE). Else the preload value is copied in the active capture/compare 4
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4). The
TIMx_CCR4 register is read-only and cannot be programmed.
24 23 22
rw/r rw/r rw/r
8 7 6
CCR3[15:0]
rw/r rw/r rw/r
24 23 22
rw/r rw/r rw/r
8 7 6
CCR4[15:0]
rw/r rw/r rw/r
DocID025202 Rev 7
21 20 19 18
rw/r rw/r rw/r rw/r
5 4 3 2
rw/r rw/r rw/r rw/r
21 20 19 18
rw/r rw/r rw/r rw/r
5 4 3 2
rw/r rw/r rw/r rw/r
RM0365
17 16
rw/r rw/r
1 0
rw/r rw/r
17 16
rw/r rw/r
1 0
rw/r rw/r