Rtc Date Register (Rtc_Dr) - STMicroelectronics RM0365 Reference Manual

RM0365
Backup domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. MNT[2:0]
rw rw
Bits 31-23 Reserved, must be kept at reset value
Bit 22 PM: AM/PM notation
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format
27.6.2

RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to
Reading the calendar on page
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x04
Backup domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31 30 29
Res. Res. Res. Res.
15 14 13
WDU[2:0]
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
MNU[3:0]
rw rw rw rw
0: AM or 24-hour format
1: PM
729.
28 27 26 25
Res. Res. Res.
12 11 10 9
MT MU[3:0]
rw rw rw rw
24 23 22
Res. Res. PM
rw
8 7 6
Res.
rw rw
Calendar initialization and configuration on page 729
730.
24 23 22
Res. YT[3:0]
rw rw
8 7 6
Res. Res.
rw
DocID025202 Rev 7
Real-time clock (RTC)
21 20 19 18
HT[1:0]
rw rw rw rw
5 4 3
ST[2:0]
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3
DT[1:0]
rw rw rw rw
17 16
HU[3:0]
rw rw
2 1 0
SU[3:0]
rw rw
and
RTC register
17 16
YU[3:0]
rw rw
2 1 0
DU[3:0]
rw rw
740/1080
764