General-purpose timers (TIM15/TIM16/TIM17)
1. The internal break event source can be:
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A clock failure event generated by CSS. For further information on the CSS, refer to
system (CSS)
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A PVD output
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SRAM parity error signal
®
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Cortex-M4
F LOCKUP (Hardfault) output
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COMP output
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Figure 238. TIM15 block diagram
DocID025202 Rev 7
RM0365
Section 9.2.7: Clock security
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