STMicroelectronics RM0365 Reference Manual page 10

RM0365
15.3.17 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 304
15.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,
15.3.19 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
15.3.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 310
15.3.21 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 311
15.3.22 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 319
15.3.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 320
15.3.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 320
15.3.25 Timing diagrams example (single/continuous modes,
15.3.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
15.3.27 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
15.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
15.3.29 Dual ADC modes (STM32F302xB/C/D/E only) . . . . . . . . . . . . . . . . . . 337
15.3.30 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
15.3.31 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
15.3.32 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 353
15.4 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
15.5 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
15.5.1
15.5.2
15.5.3
15.5.4
15.5.5
15.5.6
15.5.7
15.5.8
15.5.9
15.5.10 ADC regular sequence register 1 (ADCx_SQR1, x=1..2) . . . . . . . . . . 372
15.5.11 ADC regular sequence register 2 (ADCx_SQR2, x=1..2) . . . . . . . . . . 373
15.5.12 ADC regular sequence register 3 (ADCx_SQR3, x=1..2) . . . . . . . . . . 375
15.5.13 ADC regular sequence register 4 (ADCx_SQR4, x=1..2) . . . . . . . . . . 376
15.5.14 ADC regular Data Register (ADCx_DR, x=1..2) . . . . . . . . . . . . . . . . . 377
15.5.15 ADC injected sequence register (ADCx_JSQR, x=1..2) . . . . . . . . . . . 378
15.5.16 ADC offset register (ADCx_OFRy, x=1..2) (y=1..4) . . . . . . . . . . . . . . . 380
15.5.17 ADC injected data register (ADCx_JDRy, x=1..2, y= 1..4) . . . . . . . . . . 381
JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . 333
ADC interrupt and status register (ADCx_ISR, x=1..2) . . . . . . . . . . . . 356
ADC interrupt enable register (ADCx_IER, x=1..2) . . . . . . . . . . . . . . . 358
ADC control register (ADCx_CR, x=1..2) . . . . . . . . . . . . . . . . . . . . . . . 360
ADC configuration register (ADCx_CFGR, x=1..2) . . . . . . . . . . . . . . . 363
ADC sample time register 1 (ADCx_SMPR1, x=1..2) . . . . . . . . . . . . . 367
ADC sample time register 2 (ADCx_SMPR2, x=1..2) . . . . . . . . . . . . . 369
ADC watchdog threshold register 1 (ADCx_TR1, x=1..2) . . . . . . . . . . 369
ADC watchdog threshold register 2 (ADCx_TR2, x = 1..2) . . . . . . . . . 370
ADC watchdog threshold register 3 (ADCx_TR3, x=1..2) . . . . . . . . . . 371
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