Dma Functional Description; Dma Transactions; Figure 23. Dma Block Diagram - STMicroelectronics RM0365 Reference Manual

RM0365
12.4

DMA functional description

The block diagram is shown in the following figure.
1. DMA2, SPI1, TIM3, TIM4, UART4, UART5 and ADC2 are not available in STM32F302x6/8 devices.
2. I2C3 is not available in STM32F302xB/C devices.
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex-M4
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
12.4.1

DMA transactions

After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller

Figure 23. DMA block diagram

®
F core. The DMA request may stop the CPU access to the system bus for some
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