External Memory Interface Signals; Table 47. Programmable Nor/Psram Access Parameters; Table 48. Non-Multiplexed I/O Nor Flash Memory - STMicroelectronics RM0365 Reference Manual

RM0365
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see
The programmable memory parameters include access times (see
for wait management (for PSRAM and NOR Flash accessed in burst mode).
Parameter
Address
setup
Address hold
Data setup
Bust turn
Clock divide
ratio
Data latency
14.5.1

External memory interface signals

Table 48,
Flash memory, SRAM and PSRAM.
Note: The prefix "N" identifies the signals which are active low.
NOR Flash memory, non-multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).
Section 14.5.6: NOR/PSRAM controller

Table 47. Programmable NOR/PSRAM access parameters

Function
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the data setup
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 49 and Table 50

Table 48. Non-multiplexed I/O NOR Flash memory

FMC signal name
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
DocID025202 Rev 7
Flexible static memory controller (FSMC)
Access mode
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous and
synchronous
read/write
Synchronous
Synchronous
list the signals that are typically used to interface with NOR
I/O
O
O
I/O
O
O
O
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FMC
registers).
Table 47) and support
Unit
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
Memory clock
cycle (CLK)
Function
Clock (for synchronous access)
Address bus
Bidirectional data bus
Chip Select, x = 1..4
Output enable
Write enable
Min. Max.
0 15
1 15
1 256
0 15
2 16
2 17
234/1080
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