Memory Organization; Introduction; Memory Map And Register Boundary Addresses; Table 2. Stm32F302Xb/C Peripheral Register Boundary Addresses - STMicroelectronics RM0365 Reference Manual

3.2

Memory organization

3.2.1

Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word's least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into 8 main blocks, of 512 Mbytes each.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered "Reserved". For the detailed mapping of available memory and register areas,
refer to

Memory map and register boundary addresses

3.2.2 Memory map and register boundary addresses
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map.
The following table gives the boundary addresses of the peripherals available in the
devices.

Table 2. STM32F302xB/C peripheral register boundary addresses

Bus Boundary address
AHB3 0x5000 0000 - 0x5000 03FF
0x4800 1800 - 0x4FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
AHB2
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
47/1080
Size
Peripheral
(bytes)
1 K ADC1 - ADC2
~132 M Reserved
1 K GPIOF
1 K GPIOE
1 K GPIOD
1 K GPIOC
1 K GPIOB
1 K GPIOA
~128 M Reserved
DocID025202 Rev 7
and peripheral sections.
(1)
Peripheral register map
Section 15.6.4 on page 389
Section 10.4.12 on page 170
RM0365