Table 71. Fmc_Bcrx Bit Fields; Figure 48. Synchronous Multiplexed Write Mode Waveforms - Psram (Cram) - STMicroelectronics RM0365 Reference Manual

RM0365

Figure 48. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed
to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit No.
31-20
20
19
18-15
14
13
12
11

Table 71. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x1
Reserved 0x0
EXTMOD 0x0
to be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise.
WREN 0x1
WAITCFG 0x0
DocID025202 Rev 7
Flexible static memory controller (FSMC)
Value to set
260/1080
286