Data Management; Figure 78. Single Conversions Of A Sequence, Hardware Trigger; Figure 79. Continuous Conversions Of A Sequence, Hardware Trigger - STMicroelectronics RM0365 Reference Manual

RM0365

Figure 78. Single conversions of a sequence, hardware trigger

1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

Figure 79. Continuous conversions of a sequence, hardware trigger

1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
15.3.26

Data management

Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH,
ALIGN)
Data and alignment
At the end of each regular conversion channel (when EOC event occurs), the result of the
converted data is stored into the ADCx_DR data register which is 16 bits wide.
At the end of each injected conversion channel (when JEOC event occurs), the result of the
converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits
wide.
The ALIGN bit in the ADCx_CFGR register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in
and Figure 83.
DocID025202 Rev 7
Analog-to-digital converters (ADC)
Figure 80, Figure 81, Figure 82
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