Figure 286. Setup And Hold Timings - STMicroelectronics RM0365 Reference Manual

Inter-integrated circuit (I2C) interface
I2C timings
The timings must be configured in order to guarantee a correct data hold and setup time,
used in master and slave modes. This is done by programming the PRESC[3:0],
SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
configuration window
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Figure 286. Setup and hold timings

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RM0365