Nor Flash/Psram Controller - STMicroelectronics RM0365 Reference Manual

Flexible static memory controller (FSMC)
consecutive write operations to the address section are required to specify the full
address.
•
To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
14.5

NOR Flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:
•
Asynchronous SRAM and ROM
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–
•
PSRAM (Cellular RAM)
–
–
–
•
NOR Flash memory
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–
–
The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FMC supports a wide range of devices through a programmable timings among which:
• Programmable wait states (up to 15)
•
Programmable bus turnaround cycles (up to 15)
• Programmable output enable and write enable delays (up to 15)
•
Independent read and write timings and protocol to support the widest variety of
memories and timings
•
Programmable continuous clock (FMC_CLK) output.
The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1
register:
• If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during
synchronous accesses (Read/write transactions).
•
If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must
be configured in synchronous mode (see
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AHB data size has to be the same as the memory data width (MWID) otherwise the
FMC_CLK frequency will be changed depending on AHB data transaction (refer to
Section 14.5.5: Synchronous transactions
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8 bits
16 bits
Asynchronous mode
Burst mode for synchronous accesses
Multiplexed or non-multiplexed
Asynchronous mode
Burst mode for synchronous accesses
Multiplexed or non-multiplexed
DocID025202 Rev 7
Section 14.5.6: NOR/PSRAM controller
for FMC_CLK divider ratio formula).
RM0365