RM0365
26.4.5
Window register (IWDG_WINR)
Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 WIN[11:0]: Watchdog counter window value
These bits are write access protected see
the window value to be compared to the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
Note: Reading this register returns the reload value from the V
28
27
26
25
Res.
Res.
Res.
12
11
10
9
rw
rw
rw
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG_SR register is reset.
DocID025202 Rev 7
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
WIN[11:0]
rw
rw
rw
rw
Section
26.3.5. These bits contain the high limit of
Independent watchdog (IWDG)
20
19
18
Res.
Res.
Res.
4
3
2
rw
rw
rw
voltage domain. This value
DD
17
16
Res.
Res.
1
0
rw
rw
720/1080
721
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