Usart Register Map; Table 160. Usart Register Map And Reset Values - STMicroelectronics RM0365 Reference Manual

RM0365
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Note: This register must be written only when TXE=1.
29.8.12

USART register map

The table below gives the USART register map and reset values.
Offset Register
USART_CR1
0x00
Reset value
USART_CR2
0x04
Reset value
USART_CR3
0x08
Reset value
USART_BRR
0x0C
Reset value
USART_GTPR
0x10
Reset value
USART_RTOR
0x14
Reset value
USART_RQR
0x18
Reset value
Universal synchronous asynchronous receiver transmitter (USART)
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.

Table 160. USART register map and reset values

0 0 0 0 0 0
ADD[7:4] ADD[3:0]
0 0 0 0 0 0 0 0 0
BLEN[7:0]
0 0 0 0 0 0 0 0 0
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315).
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
STOP
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
BRR[15:0]
0 0 0 0 0 0 0 0 0
GT[7:0]
0 0 0 0 0 0 0 0 0
RTO[23:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0
0 0 0 0 0 0
0 0 0 0 0 0
PSC[7:0]
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
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901