Clock Generator; Figure 376. Audio Sampling Frequency Definition; Figure 377. I - STMicroelectronics RM0365 Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
30.7.5

Clock generator

2
The I S bit rate determines the data flow on the I
frequency.
2
I S bit rate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I
2
I S bit rate = 16 × 2 × f
It will be: I
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
1. Where x can be 2 or 3.
Figure 377
always the system clock. To achieve high-quality audio performance, the I2SxCLK clock
source can be an external clock (mapped to the I2S_CKIN pin). Refer to
Clock configuration register
The audio sampling frequency may be 192 KHz, 96 kHz or 48 kHz. In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
939/1080
S
2
S bit rate = 32 x 2 x f

Figure 376. Audio sampling frequency definition

Figure 377. I

presents the communication clock architecture. By default, the I2Sx clock is
(RCC_CFGR).
DocID025202 Rev 7
2
S data line and the I
2
S bit rate is calculated as follows:
if the packet length is 32-bit wide.
S
2
S clock generator architecture
RM0365
2
S clock signal
Section 9.4.2: