Adc Watchdog Threshold Register 2 (Adcx_Tr2, X = 1 - STMicroelectronics RM0365 Reference Manual

RM0365
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 1.
Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
15.5.8

ADC watchdog threshold register 2 (ADCx_TR2, x = 1

Address offset: 0x24
Reset value: 0x00FF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 2.
Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT2[7:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 2.
Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
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