Adc Interrupt Enable Register (Adcx_Ier, X=1 - STMicroelectronics RM0365 Reference Manual

RM0365
15.5.2

ADC interrupt enable register (ADCx_IER, x=1

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 JQOVFIE: Injected context queue overflow interrupt enable
This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt.
0: Injected Context Queue Overflow interrupt disabled
1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit
is set.
Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected
conversion is ongoing).
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 3 interrupt disabled
1: Analog watchdog 3 interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 2 interrupt disabled
1: Analog watchdog 2 interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.
0: Analog watchdog 1 interrupt disabled
1: Analog watchdog 1 interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of injected sequence of conversions
interrupt.
0: JEOS interrupt disabled
1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected
conversion is ongoing).
28 27 26 25
Res. Res. Res.
12 11 10 9
JQ AWD3
Res.
OVFIE IE
rw rw
24 23 22
Res. Res. Res.
8 7 6
AWD2 AWD1
JEOSIE JEOCIE OVRIE
IE IE
rw rw rw
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Analog-to-digital converters (ADC)
2)
..
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
EOSIE EOCIE
rw rw rw rw
17 16
Res. Res.
1 0
EOSMP ADRDY
IE IE
rw rw
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