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Independent watchdog (IWDG)
26.4.2
Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected see
written by software to select the prescaler divider feeding the counter clock. PVU bit of
IWDG_SR must be reset in order to be able to change the prescaler divider.
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
717/1080
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Section 26.3.5: Register access
DocID025202 Rev 7
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
protection. They are
RM0365
17
16
Res.
Res.
1
0
PR[2:0]
rw
rw
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