Nand Flash/Pc Card Controller Registers - STMicroelectronics RM0365 Reference Manual

RM0365
PWAITEN bit in the FMC_PCRx register. To detect correctly the nWAIT assertion, the
MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:
where max_wait_assertion_time is the maximum time taken by NWAIT to go low once
nOE/nWE or nIORD/nIOWR is low.
After WAIT de-assertion, the FMC extends the WAIT phase for 4 HCLK clock cycles.
14.6.8

NAND Flash/PC Card controller registers

PC Card/NAND Flash control registers 2..4 (FMC_PCR2..4)
Address offset: 0x40 + 0x20 * (x – 1), x = 2..4
Reset value: 0x0000 0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:20 Reserved, must be kept at reset value
Bits 19:17 ECCPS: ECC page size.
Defines the page size for the extended ECC:
Bits 16:13 TAR: ALE to RE delay.
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 12:9 TCLR: CLE to RE delay.
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value
Bit 6 ECCEN: ECC computation logic enable bit
xxWAITx
ECCPS
rw rw rw rw rw rw rw rw rw rw rw
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Flexible static memory controller (FSMC)
max_wait_assertion_time
≥
4
+ ------------------------------------------------------------------ -
HCLK
TAR
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9 8 7 6 5
TCLR PWID
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4 3 2 1 0
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