Timer Synchronization (Tim15); Debug Mode - STMicroelectronics RM0365 Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)
22.4.20

Timer synchronization (TIM15)

The TIMx timers are linked together internally for timer synchronization or chaining. Refer to
Section 21.3.19: Timer synchronization
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
22.4.21

Debug mode

When the microcontroller enters debug mode (Cortex-M4
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
watchdog, bxCAN and
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are
disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state
(OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force
them to Hi-Z.
653/1080
for details.
I2C.
DocID025202 Rev 7
®
F core halted), the TIMx counter
Section 33.14.2: Debug support for timers,
RM0365