Clock Configuration Register (Rcc_Cfgr) - STMicroelectronics RM0365 Reference Manual

RM0365
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit
cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
Bits 15:8 HSICAL[7:0]: HSI clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: HSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that
influence the frequency of the HSI.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz
± 1%. The trimming step (F
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: HSI clock ready flag
Set by hardware to indicate that HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI oscillator clock cycles.
Bit 0 HSION: HSI clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving Stop or Standby mode or in case
of failure of the HSE crystal oscillator used directly or indirectly as system clock. This bit
cannot be reset if the HSI is used directly or indirectly as system clock or is selected to become
the system clock.
9.4.2

Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29
MCOF /
PLLNO
MCOPRE[2:1] MCOP
DIV
RE0
rw rw rw r / rw
15 14 13
PLLSR
Res PPRE2[2:0]
(1)
C
rw rw
1. STM32F302xD/E only
0: HSE oscillator OFF
1: HSE oscillator ON
0: HSI oscillator not ready
1: HSI oscillator ready
0: HSI oscillator OFF
1: HSI oscillator ON
wait state 2, word, half-word and byte access
≤ ≤
28 27 26 25
Res MCO[2:0]
rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
) is around 40 kHz between two consecutive HSICAL steps.
hsitrim
24 23 22
USBPR
I2SSRC
E
rw rw rw
8 7 6
HPRE[3:0]
rw rw rw
DocID025202 Rev 7
Reset and clock control (RCC)
21 20 19 18
PLLMUL[3:0]
rw rw rw rw
5 4 3 2
SWS[1:0]
rw rw r r
17 16
PLL PLL
XTPRE SRC
rw rw
1 0
SW[1:0]
rw rw
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