STMicroelectronics RM0365 Reference Manual page 957

Serial peripheral interface / inter-IC sound (SPI/I2S)
Bit 3 CKPOL: Inactive state clock polarity
2
0: I S clock inactive state is low level
2
1: I S clock inactive state is high level
Note: For correct operation, this bit should be configured when the I
It is not used in SPI mode.
The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and
WS signals.
Bits 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I
They are not used in SPI mode.
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in.
Note: For correct operation, this bit should be configured when the I
It is not used in SPI mode.
957/1080 DocID025202 Rev 7
RM0365
2
S is disabled.
2
S is disabled.
2
S is disabled.