Dma Registers; Dma Interrupt Status Register (Dma_Isr) - STMicroelectronics RM0365 Reference Manual

RM0365
12.5

DMA registers

Refer to
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-
bit).
12.5.1

DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
TEIF4 HTIF4 TCIF4 GIF4
r r r
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1..7)
11, 7, 3
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1..7)
10, 6, 2
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1..7)
9, 5, 1
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1..7)
8, 4, 0
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
Section 2.1 on page 42
28 27 26 25
TEIF7 HTIF7 TCIF7
r r r
12 11 10 9
TEIF3 HTIF3 TCIF3
r r r r
Direct memory access controller (DMA)
for a list of abbreviations used in register descriptions.
24 23 22
GIF7 TEIF6 HTIF6
r r r
8 7 6
GIF3 TEIF2 HTIF2
r r r
DocID025202 Rev 7
21 20 19 18
TCIF6 GIF6 TEIF5 HTIF5
r r r
5 4 3 2
TCIF2 GIF2 TEIF1 HTIF1
r r r
17 16
TCIF5 GIF5
r r r
1 0
TCIF1 GIF1
r r r
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