S0: I-Bus; S1: D-Bus; S2: S-Bus; S3, S4: Dma-Bus - STMicroelectronics RM0365 Reference Manual

System and memory overview
3.1.1

S0: I-bus

This bus connects the Instruction bus of the Cortex
used by the core to fetch instructions. The targets of this bus are the internal Flash memory
and the SRAM.
3.1.2

S1: D-bus

This bus connects the DCode bus (literal load and debug access) of the Cortex
the BusMatrix. The targets of this bus are the internal Flash memory and the SRAM.
3.1.3

S2: S-bus

This bus connects the system bus of the Cortex
used to access data located in the peripheral or SRAM area. The targets of this bus are the
SRAM, the AHB to APB1/APB2 bridges, the AHB IO port and the 2 ADCs.
3.1.4

S3, S4: DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of different Masters to Flash, SRAM and peripherals.
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Figure 3. STM32F302xD/E system architecture

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-M4 core to the BusMatrix. This bus is
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-M4 core to the BusMatrix. This bus is
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-M4 core to