Table 145. Smbus With Pec Configuration - STMicroelectronics RM0365 Reference Manual

Inter-integrated circuit (I2C) interface
Specific address (Slave mode)
The specific SMBus addresses should be enabled if needed. Refer to
page 802
•
The SMBus Device Default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus Host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
•
The Alert Response Address (0b0001100) is enabled by setting the ALERTEN bit in the
I2C_CR1 register.
Packet error checking
PEC calculation is enabled by setting the PECEN bit in the I2C_CR1 register. Then the PEC
transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the I2C_CR2
register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES-1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.
Master Tx/Rx NBYTES + PEC+ STOP
Master Tx/Rx NBYTES + PEC + ReSTART
Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the
I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification version 2.0.
•
t
TIMEOUT
In order to enable the t
programmed with the timer reload value in order to check the t
TIDLE bit must be configured to '0' in order to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA+1) x 2048 x t
flag is set in the I2C_ISR register.
Refer to
(max tTIMEOUT = 25
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
• t
LOW:SEXT
Depending on if the peripheral is configured as a master or as a slave, The 12-bit
TIMEOUTB timer must be configured in order to check t
803/1080
for more details.

Table 145. SMBUS with PEC configuration

Mode
Slave Tx/Rx with PEC
check
TIMEOUT
Table 146: Examples of TIMEOUTA settings for various I2CCLK frequencies
ms).
and t check
LOW:MEXT
DocID025202 Rev 7
SBC bit RELOAD bit AUTOEND bit PECBYTE bit
x 0
x 0
1 0
check, the 12-bit TIMEOUTA[11:0] bits must be
Bus idle detection on
1
0
x
parameter. The
TIMEOUT
, the TIMEOUT
I2CCLK
for a slave and
LOW:SEXT
RM0365
1
1
1