STMicroelectronics RM0365 Reference Manual page 37

List of figures
Figure 248. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 630
Figure 249. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 250. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 251. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 252. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 633
Figure 253. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 254. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Figure 255. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 634
Figure 256. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Figure 257. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 258. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Figure 259. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 260. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 261. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 642
Figure 262. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 642
Figure 263. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 264. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 265. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 266. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 267. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Figure 268. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Figure 269. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 270. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 695
Figure 271. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 695
Figure 272. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 273. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 274. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 275. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 276. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 277. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 278. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 700
Figure 279. IR internal hardware connections with TIM16 and TIM17. . . . . . . . . . . . . . . . . . . . . . . . . 706
Figure 280. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Figure 281. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Figure 282. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Figure 283. RTC block diagram
Figure 284. I2C block diagram
Figure 285. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Figure 286. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
Figure 287. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Figure 288. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 289. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Figure 290. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Figure 291. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . . 781
Figure 292. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . . 782
Figure 293. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Figure 294. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 784
Figure 295. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 785
Figure 296. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 297. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
37/1080
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
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