STMicroelectronics RM0365 Reference Manual page 154

Advanced arm-based 32-bit mcus
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RM0365
Offset
Register
RCC_BDCR
0x20
Reset value
RCC_CSR
0x24
Reset value
RCC_AHBRSTR
0x28
Reset value
RCC_CFGR2
0x2C
Reset value
RCC_CFGR3
0x30
Reset value
1. On STM32F302xB/C devices only.
2. On STM32F302x6/8 devices only.
3. On STM32F302xD/E only
Refer to
boundary addresses.
Table 29. RCC register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
Section 3.2.2: Memory map and register boundary addresses
0
0
0
0
0
0
0
0
0
0
0
0
DocID025202 Rev 7
Reset and clock control (RCC)
RTC
SEL
[1:0]
0
0
ADC12PRES
[4:0]
0
0
0
0
0
0
0
for the register
LSE
DRV
[1:0]
1
1
0
0
0
0
0
PREDIV[3:0]
0
0
0
0
154/1080
154

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