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CHAPTER 19 16-BIT PPG TIMER
19.7 Registers
19.7.2
16-bit PPG Cycle Setting Buffer Register (Upper/
Lower) (PCSRHn/PCSRLn)
The 16-bit PPG cycle setting buffer registers are used to set the cycle for the
output pulses generated by the PPG.
■ Register Configuration
PCSRHn
bit
7
Field
CS15
Attribute
R/W
Initial value
1
PCSRLn
bit
7
Field
CS07
Attribute
R/W
Initial value
1
■ Register Functions
These registers form a 16-bit register which sets the period for the output pulses generated by
the PPG. The values set in these registers are loaded to the downcounter.
When writing to these registers, always use one of the following procedures.
• Use the "MOVW" instruction (use a 16-bit access instruction to write to the PCSRHn
register address).
• Use the "MOV" instruction and write to PCSRHn first and then PCSRLn.
If a downcounter load occurs after writing data to PCSRHn (but before writing data to
PCSRLn), the previous valid PCSRHn/PCSRLn value will be loaded to the downcounter. If
the PCSRHn/PCSRLn value is modified during counting, the modified value will become
effective from the next load of the downcounter.
• Do not set PCSRHn and PCSRLn to "0x00", or PCSRHn to "0x01" and PCSRLn to "0x01".
Note:
If the downcounter load occurs after the "MOV" instruction is used to write data to
PCSRLn before PCSRHn, the previous valid PCSRHn value and newly written PCSRLn
value are loaded to the downcounter. It should be noted that as a result, the correct
period cannot be set.
346
6
5
CS14
CS13
R/W
R/W
1
1
6
5
CS06
CS05
R/W
R/W
1
1
FUJITSU SEMICONDUCTOR LIMITED
4
3
CS12
CS11
R/W
R/W
1
1
4
3
CS04
CS03
R/W
R/W
1
1
MB95630H Series
2
1
CS10
CS09
R/W
R/W
1
1
2
1
CS02
CS01
R/W
R/W
1
1
MN702-00009-1v0-E
0
CS08
R/W
1
0
CS00
R/W
1
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