IOWR0 to IOWR3 (I/O Wait Registers for DMAC)
This section describes the I/O wait registers for DMAC in detail.
■ Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3)
The configuration of IOWR0 to IOWR3 is shown below:
RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00 xxxxxxxx
RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10 xxxxxxxx
RYE2 HLD2 WR21 WR20 IW23 IW22 IW21 IW20 xxxxxxxx
RYE3 HLD3 WR31 WR30 IW33 IW32 IW31 IW30 xxxxxxxx
Note : The MB91F355A/355A/354A/F356B/F357B series have IOWR3 only.
These registers are used to set various waits for DMA fly-by access.
[Bits 31, 23, 15] RYE0,1,2 (RDY function setting: ReadY Enable 0,1,2,3)
These bits set the wait control using RDY for channels 0 to 2 at DMA fly-by access.
When "1" is set, wait insertion by the RDY pin can be performed during fly-by transfer on the relevant
channel. IOWR and IORD are extended until the RDY pin is enabled. Also, RD/WR0-WR3/WR on the
memory side are extended synchronously.
If the chip select area of the fly-by transfer destination is set to RDY-enabled in the ACR register, wait
insertion by the RDY pin can be performed regardless of the RYEn bit of IOWR side. When the chip select
area of the fly-by transfer destination is set to RDY-disabled in the ACR register, wait insertion by the
RDY pin can only be performed during fly-by access if the area is set to RDY-enabled by the RYEn bit on
the IOWR side.
Disable RDY input for I/O access.
Enable RDY input for I/O access.
RDY function setting