Timer State Control Register (Tccsh, Tccsl) - Fujitsu MB91260B Series Hardware Manual

11.4.3

Timer State Control Register (TCCSH, TCCSL)

The timer state control register (TCCSH, TCCSL) is a 16-bit register which is used to
control the operation of the 16-bit free-run timer.
■ Timer State Control Register, Upper Byte (TCCSH)
Timer state control register (Upper)
Bit15 Bit14
ECKE IRQZF
R/W
R/W: Readable/Writable
: Initial value
Bit13 Bit12 Bit11
IRQZE MSI2 MSI1
R/W R/W R/W
CHAPTER 11 MULTIFUNCTIONAL TIMER
Bit10 Bit9
MSI0 ICLR ICRE
R/W R/W R/W
ICRE Compare clear interrupt request enable bit
0 Disable interrupt request
1 Enable interrupt request
Compare clear interrupt flag bit
ICLR
Read
0 No compare clear match
1 Compare clear matches
MSI2 MSI1 MSI0
0 0 0 Generate interrupt at 1st match occurred
0 0 1 Generate interrupt at 2nd match occurred
0 1 0 Generate interrupt at 3rd match occurred
0 1 1 Generate interrupt at 4th match occurred
1 0 0 Generate interrupt at 5th match occurred
1 0 1 Generate interrupt at 6th match occurred
1 1 0 Generate interrupt at 7th match occurred
1 1 1 Generate interrupt at 8th match occurred
IRQZE Zero detection interrupt request enable bit
0 Disable interrupt request
1 Enable interrupt request
Zero detection interrupt flag bit
IRQZF
Read
0 Zero is not detected
1 Zero is detected
ECKE
0 Internal clock
1 External clock
Bit8
TCCSH
Address: 0000A8
R/W
Initial value: 00000000
Write
Clear this bit
No effect this bit
Interrupt mask selection bit
Write
Clear this bit
No effect on this bit
Clock select bit
H
B
221